1. Technical Field of the Invention
The present invention relates to Programmable Logic Devices (PLDs) and more particularly to a device and method for configuration of PLDs.
2. Description of Related Art
A typical field programmable gate array (FPGA) comprises an array of configuration memory cells, configuration control elements and a matrix of logic and I/O blocks. Different digital circuits can be realized on an FPGA by configuring its memory cell array and control elements.
FIG. 1 shows a block diagram of a typical FPGA 100 comprising an array of configuration memory cells 1.1 (also referred to as the core or latch array) connected to a Vertical Shift Register (VSR) 1.2, a select register (SR) 1.3, and a horizontal decoder 1.4 providing its output to the SR 1.3. The decoder 1.4 receives its input from a configuration state machine 1.5 which also provides input to VSR 1.2 and incorporates a counter register 1.5.1 and index register 1.5.2.
An FPGA is typically configured as follows: a frame of data is loaded into the VSR 1.2. For a complete frame of data that is loaded in the VSR 1.2, the configuration state machine 1.5 and the selection register 1.3 enable a selection line for shifting the data column from VSR 1.2 to a particular column of the configuration memory latch array 1.1 and on completion of the shift operation the selection lines are disabled. The next frame of data is then loaded in the VSR 1.2 and the process of selecting and shifting is repeated until the entire latch array 1.1 is configured.
The configuration state machine 1.5 supports two types of configuration schemes. One is a normal configuration, in which the entire configuration latch array 1.1 matrix is loaded. The other scheme is the partial configuration scheme, in which only a part of configuration latch array 1.1 matrix needs to be reloaded. In order to support both schemes, the configuration state machine includes two registers namely count register 1.5.1 and the index register 1.5.2 as shown in FIG. 1. In case of the normal operation for configuration, all the configuration latches 1.1 are first initialized to the reset value, and then the count register 1.5.1 is initialized to the first location. The index register 1.5.2 is initialized to the maximum number of select lines in the configuration latch matrix. The data is loaded into the VSR until the VSR is full. After the VSR is full one of the select lines is enabled depending on the value stored in the count register, thus transferring the data from the VSR register into the selected column of configuration latches.
After the data has been written onto the latches 1.1, the value of counter register 1.3 is incremented and the value in the index register 1.4 is decremented. This process continues until the value stored in the index is zero. After completion of the configuration process the startup sequence is initiated.
As described above, the index register 1.5.1 stores the value of the columns of configuration latches 1.1 to be enabled. Thus in case of partial configuration the value stored in this register determines the number of columns to be reprogrammed.
Decoder 1.4 and a select register 1.3 are used for enabling the column of latches. The line to be enabled is the decoded output of count register 1.5.1. Since the number of column lines of configuration latches 1.1 is very high (of the order of 1000) the complexity of decoder 1.4 is very high, and the placement and routing of the decoder 1.4 is also complex. The area consumed in making such a large decoder 1.4 is also high.
A further problem associated with this technique is the difficulty in scalability. Any modification in the size of the array requires a change in the size of the decoder.
Thus, there is a need to develop a technique that provides a simple method of enabling the column of configuration latches and also reduces area, complexity and routing requirements of the decoder.